p'" jig 7 {() f analog 8-, 10-, 12-bit video speed w devices current and voltage out, d / a converters 7 fea tures current settling times to 15ns :t1.5v compliance voltage settling times to 100ns (mdh) monotonicity guaranteed over temperature high output currents - 15ma -30c to +85c operating range industry standard pin outs 20v, p.p out (mdh) ttl or ecl logic applications crt vector displays digitial waveform generation automatic test equipment tv picture reconstruction general description this broad family of digital-to-analog converters represents the "state of the art" in modular, high speed, voltage and current output devices. the family consists of a total of 11 devices in 4 series (mds, mdse, mdsl and mdh) that allow the user to make engineering trade-offs between resolution, speed, output and logic type. the first 3 are high compliance current output units which make possible linear output swings greater than :t1.5v. the voltage output mdh series contain a fast settling hybrid operational amplifier which provides:t 10v output at :t5oma. to simplify selection these major specifications are summarized in table 1. speed with precision analog devices' model mds-1240 is the first d/a converter available with highly reliable, internal hybrid construction to ,. achieve ultra-high speed operation. in fact, it is the fastest 12- bit d/a available, settling to 0.025% in 40ns. hybrid construc- tion eliminates the thermal lag problem inherent in 12-bit d/a's constructed with discrete components. this in turn means that the accuracy is maintained over the total frequency range of operation, yielding superior results for frequency do- main applications. the mds-1240 is particularly well suited for crt display ap- plications because of its unsurpassed speed and drive capa- bilities. the high output current (isma) allows the use of low impedance loads so that settling times remain short - even with higher output voltage levels. the ability to drive load ca- pacitance is at least 3 times that of other 12-bit d/a's thus providing capability to drive a terminated transmission line directly. the mds-815 and mds-i020 provide similar per- formance at 8 and 10 bits, while the mds-e units provide it with ecl logic. mdsl-082s, mdsl-i035 and mdsl-12s0 also utilize this reliable hybrid construction. the use of laser trimmed resistor networks within the d/a's not only elimi- nates thermal time lag errors but provide the linearity temp- co of 2ppmtc; guaranteeing monotonic operation over the extended temperature range of -30c to +8soc. the power dissipation of the mdsl series is one-half that of competi- tive d/a's, but a full sma output current is maintained. this allows driving transmission lines or other low impedance loads directly. (continued on page 1955) d/a converters 1915 ',:-",~,,"", ,'c ,:c';'" -:", ~",;:",,":_'.,-: :-" "".':_-"_:'.~,':,,-:.:.c'-, full scale full scale input model bits output settling time logic (fastest settling high current out) mds-0815 8 15ma 15ns to 0.4% fs ttl mds-i020 to 15ma 20n5 to 0.1% fs ttl mds-1240 12 15ma 40n5 to 0.025% fs ttl (mds with ecl logic) mds-o815e 8 15ma 15ns to 0.4% fs ecl mds-i020e 10 15ma 20n5 to 0.1% fs ecl (low current mds) mdsl-0825 8 sma 25n5too.l% ttl mdsl-i035 10 sma 25n5too.l% ttl mdsl-1250 12 sma sons to 0.025% ttl (voltage out mdsl) mdh-0870 8 10v /50ma 150n5 to 0.4% ttl mdh-l00l 10 ,tov /50ma 200n5 to 0,1 % ttl mdh-1202 12 tov /50ma 500n5 to 0.025% ttl table 1. page 1 of 8 obsolete
',',:' <,:'"",..:,~.~,,':".,':<""",-,;",.,::,,:,::;,.:,.',,',:,,':;:":'.-:.' ,;,:' ",:"',',", specifications (typical @ +25c unless otherwise specified) .specifications same as mds~81s. notes, 1 ippmt' c for current output, op amp is solly / c. (see tables in figures 15. 16 and 17, for overall tc in various configurations.) 'for full scale step. '0 to +5v out f '0 to +10v out see figures 15 and 16 for test circuits. 'tsv out specifications subject to change without notice, 1925 d/a converters current output current output mds mds-e (ecl) model units 0815 1020 1240 0815 1020 resolution bits 8 10 12 8 10 lsb (weight) ila 58.6 14.6 3.66 58.6 14.6 accuracy initial (adjust to 0) :!:%fs 0.2 0.05 0.012 0.2 0.05 linearity (integral) lsb max :!:li2 . . . . monotonicity guaranteed over operating temp range ' . zero offset (adjust to 0) isna max ' . . . temperature coefficients linearity ppm/c 5 . 2 . 2 gain ppm/c 30 . 20 . . offset (ipolar) ppm/c 15 . . . . stability with time :!:%/yrmax 0.5 . . . . data inputs logic comparability ttl " ecl ecl logic voltage levels bitonlogic"i" v +2 to +5.0 ' . -0.9 -0.9 bit off logic "0" v 0 to +0.4 ' . -1.7 -1.7 logic current (each bit) bitonlogic"i" jla ';;; 50 . . . . bit off logic "0" ma -8 . -5 max . . msb ma n/a . -10 max . . coding all units binary (bin) for unipolar, . . offset binary (obn) for bipolar . . output current range unipolar ma oto+15 ' . oto-15 0 to -15 bipolar ma :!:7.5 . . . . impedance (see figure 3) n 165 . 200:!: 1 % . . compliance (mdh vout) v +1.5,-2 ' . -1.5, +2 -1.5, +2 load resistance for vout (see figure 5) oro+lv n 112 . 100 . . :!:iv n 4.32k ' 750 . . internal reference voltage out v n/a . -6.2 :!:5% ' . settling time2 current ns to %. is to 0.4 20 to 0.10 20 to 0.1 ' 20 to 0.10 40 to 0.025 unipolar voltage (rl = 300n ii 10pf) ns to % bipolar voltage (rl = 2325n iii0pf) ns to % power requirements range v :!:11 to :tl6 ' :!:14.5 to :!:16.5 . . current at nominal +v ma max 105 120 55 . 120 current at nominal -v ma max is . 20 . . power supply rejection ratio %/v 0.04 ' . . +15v "la/v -0.0001 -15v (bipolar) %/v -0.002 -15v (unipolar) %/v -0.2 temperature range operating c -20 to +75 ' -30 to +85 ' . storage c -55 to +85 ' -55 to +125 ' . case diallyl phthalate per mil-m-14 type sdg-f ' . price (1-4) $ lis 137 149 129 149 page 2 of 8 obsolete
-6.2 :t5% -6.2 :t5% -6.2 :t5% -6.2 :t5% -6.2 :t5% , -6.2 :t5% ~-- d/a converters 1935 . .~- -~ --- current output voltage out mdsl mdh 0825 1035 1250 0870 1001 1202 8 10 12 8 10 12 19.6 4.88 1.22 depends on v out 0.2 0.05 0.012 0.2 0.05 0.012 . . . . . . . . . . . . . . . lomv 10mv 10mv 2 2 2 2 2 2 20 20 20 20 20 20 . . . see note 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.6 -1.6 -1.6 -1.6 -1.6 -1.6 . . . . . . . . . . . . . . . . . . 0 to +5 0 to +5 0 to +5 :t50 max :t50 max :t50 max :t2.5 :t2.5 :t2.5 :t50 max :t50 max :t50 max 600:tl% 600:t1% 600:t 1 % 0.1 max 0.1 max 0.1 max . . . :t10 :t10 :t10 300 300 300 n/a n/a n/a 2.325k 2.325k 2.325k n/a n/a n/a 25 to 0.1 25 to 0.1 50 to 0.25 115(00.2 25 to 0.10 50 to 0.25 45 to 0.4 70 to 0.1 70 to 0.1 i 70 to 0.43 100 to 0.13 200 to 0.0253 70 to 0.1 80 to 0.05 90 to 0.025 150 to 0.44 200 to 0.14 400 to 0.0254 75 to 0.4 100 to 0.1 100 to 0.1 100 to 0.45 l30tao.15 250 to 0.0255 100 to 0.1 110 to 0.05 125 to 0.025 :t12to:t15 :t12to:t15 :tl2 to :tis :t14.5 to :t16.5 :t145 to :t16.5 :t14.5 to :t16.5 26 26 26 50 50 50 16 16 16 35 35 35 0.0001 0.0001 0.0001 0.003 0.003 0.003 0.001 0.001 0.001 0.01 0.01 0.01 0.2 0.15 0.15 0.15 0.15 0.15 -30 to +85 -30 to +85 -30 to +85 -30 to +85 -30 to +85 -30 to +85 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125 . . . . . . 112 119 129 204 214 224 page 3 of 8 obsolete
mds-o815, 0815e, 1020, 1020e outline dimensions dimensions shown l'1 inches and (rom). 2.3 (58.01 mo""" mos-'o2o mos-cio'" mos-'...' 0.43 "o.") 1- + 0.0411.0210ia mil i 23 ;58.01 i wiiil bottom view _ii -, r-.' 12.54igrio dot on top indicates position of pin ,. t1 ' mating socket msb-11713 pin designations mds-o81 5e, 1020e digital inputs 1",581 bit 1 bit2 bit 3 bit 4 bits bit 6 bit7 bits bit 9 bit 10 (lsbi mds and mdse block diagram digital inputs msb bit 1 i i i i i i i i i i i i i i bit 12 lsb hybrid current output dia converter md5-1240, mdsl-o825, 1035, 1250 outline dimensions dimensions shown in inches and (mm). 2.0 150.8) ---j --l .l mos.'2.. mosl.'035 mosl1 i 1 i i 1 i 1 1 i i 1 3 i 7 2.0 (50..' ' i 0.25 16.4' j .l ,. .- oottomview -11- 0.1(254) grid oot on top indicates position of pin ,. pin function pin function 3 bit 1 input (msbi 15 bit 11 input 4 bit 2 input 16 bit 12 input 5 bit 3 input 17 reference input 6 bit 4 input 18 reference output 7 bit 5 input 28 analog output 10 bit 6 input 29 offset 11 bit 7 input 30 ground 12 bit 8 input 31 -15v power input 13 bit 9 input 32 +15v power input 14 bit 10 input 14 ---coutput 12 offset common common pin function pin function 3 bit 1 input (msb) 17 reference ifiiput 4 bit 2 input 18 reference output 5 bit 3 input 22 analog output 6 bit 4 input 24 +input 7 bit 5 input 25 -input 10 bit 6 input 26 fixed gain 11 bit 7 input 28 current output 12 bit 8 input 29 offset 13 bit 9 input 30 ground 14 bit 10 input 31 -15v power input 15 bit 11 input 32 +15v power input 16 bit 12 input gt 24 - +in 22 ";8; tlov (max) 'soma (maxi 25 - -in fixed gain page 4 of 8 obsolete
mdh series applications by using external feedback resistor and capacitor as shown in figures 15 and 16, other full scale output ranges from 2v to 10v may be obtained. digitial inputs +1sv } mavbe omitted msb bit 1 i i i i i i i i i i i bit 12 lsb mdh dia converter vo . up to 10v >6oma output current isee belowi soon } fs adj 30 - ~~d dutput -16v +16v notes' 1. value of c is approximate. a fixed capacitor with tolerance of >1pf mav be used if 601< degradation of settling time is permitted if settling time is to be optimized,an adjustable capaci- tor should be used for c and adjusted for minimum settling time. 2. offset nulling mav be accomplished bv connecting a 1ok potentiometer between +16v and -16v, and connecting its adjust- able t;.p to a 1ok resistor. the other end of the resistor is connected to pin 2b. tvpical uncompensated offset is '" of full scale. 19b5 dia converters msb ft digital ll inputs i i i i bit 12 lsb . use inverter or ff afar 2's compl. 1', digital inputs i' -. ..." ,,! 4 '5 i '7 ill ~~:: ill converter 12 i3 i4 is ii +input 20011 offset adj 29 _offset 24 -16v +1sv notes' 1. tho 200n potentiometer is adjusted for an cutput of -fs with all zeroes in the digital input. 2. the soon potentiometer is adjusted for an output of +f5-1lsb with all one's in the digital input. 3. for two's complement 12sc! operation, an external inverter must be used to complement bit 1imsbi- 4. an adjustable capacitor mav be used for c and adjusted to optimize set- tling time. voltage settling offset r c output time tempco 0 to +2v 70ns loov/c 2k 10pf 0 to +5v loons 250vfc 8k 2pf oto+lov 200ns 500v!'c 18k 0.5pf figure 15. binary coding unipolar output configuration voltage settling offset output time tempco rl c r :tlv 70ns 100v fc 383 lopf 2k :t2v loons 200v /c 383 2pf 6k :t5v loons 250vfc 9.1k 2pf 8k :tlov 200ns 500vfc 9.1k 0.5pf 18k figure 16. offset binary coding or 2'$ comp coding bipolar output configuration page 5 of 8 obsolete
(mds-1240, mdsl-0825, 1035, 1250 continued) digitial inputs mse bit 1 i i i i i i i i i i i bit 12 lsb r1 soon zero dia converter output 11v fs 2.321<11(75011 mos.i240) grouno ref in 31 32 -15v +15v calibration procedure with input code 000000000000 adjust the sooi1 (ri) potentiometer for -1.0000 volts output. with input code 1111 i 1111111 adjust the 10011 (rzi potentiometer for +0.99976 volts output. figure 70. bipolar current output voltage output mds/mdse-81s, 1040 '.~ [ ?::~1 bit2~ digital i inputs i bit s o:il bit 10 - 10 ilsb) 12 offset dia converter figure 77. voltage output mds-1240, mdsl (all) digitial inputs msb bit i i i i i i i i i i i i bit 12 lsb ground ri 26 voltage output (vou, . -ri x 101 dia converter r3 } ext loon fs to 1kn adj ref in note, for unipolar vol tage output connect jumper between pins 29 and 30. for bipolar voi.tage output connect a sooi1 potentio. meter between pins 28 and 29 and adjust for zero output with 100000000000 input. /'" figure 72. inverting unipolar or bipolar voltage output mdsl see note -15v "5\' digitial inputs msb bit 1 i i i i i i i i i i i bit 12 lsb notes, ,. circuit shown for unipolar positive output. output settling time is approxi. mately lsons. 2. for oto +iov output r2- 30011, ri=skl1. 3. r3 is adjusted for desired output, range is approximately +5%. voltage output vou, . r111nkoi +1 volts fs unipolar 110v (maxi at 1100ma ground 4. for bipolar output connect 50011 potentiometer between pins 29 and 28 and unground pin 29. r2isse1..1o 2.32kl1, and vout (p-p) = 2 (ri iin wi "1, 5. ciis approximately lopf and may be adjusted for best transient response, figure 73. noninverting unipolar or bipolar voltage output applica nons digital inputs msb i i i i i i i i i i i lsb 14574 input register msb 3 ---. :[ ..f. 1 it 11 i2 i3 14 15 lsii16 strobe stwbe r-l -i~~ i- ~6'~ ~6f:~~;':;;c'y"mh' -'5v,'5v mds. 1240 '3 output voltage settling time. 20no } two outputs up to 2v (f-p) dgm 1040 r2 200n 9 notes on deglitched d/a, ,. consult dgm data sheet for deglitch circuit details. 2. r' is varied to obtain desired output level for 0 to'w out. put, r'. ,oon. figure 74. ultra high-speed deglitched d/a -~ d/a converters 1975 r2 300n i dia converter . - - 18 ref out r3 } ext sooi1 fs adj ref in page 6 of 8 obsolete
analog output bipolar, noninverting +fs,-llsb +1/2 fs 0 -1/2 fs -fs offset binary 111 1 110 0 100 0 010 0 000 0 analog output unipolar, noninverting +fs, -llsb +3/4 fs + 1/2 fs + 1/4 fs 0 table 2. input coding "b" trace 2omv/div "a" trace 2v/div 5ns - div figure 2. internal current dac characteristics ' 1 i i i i i i i / ,-a'to 10 i l-i j roffset 20 current controlled by input digital code offset 'output ground . figure 3. current equivalent circuit r , i roffset i i i i i l- zo j voltage controlled by digital input code offset output ground figure 4. voltage equivalent circuit 1.5 > i ~ is > 0.5 200 250 300 rl - 1! 350 4("",; 3k 2- 4- figure 5. vout vs. load resistance mds.0815, -1020 1965 d/a converters "",-~;.;.~.._~ oj! 0.1 ~ 0.7 .. 0.6 .. 0.5 i "0.4 0.3 0.2 0,1 straight binary 111 1 110 .. 0 100 0 010 0 000 0 10 15 time.. ns 20 2s figure 6. accuracy vs. time - mds and mdse basic connections and calibrations mds/mdse-o815.1020 { ~~~b,j bit 2 digital inputs bit 9 bit 10 ilsbi [ \:'i~1 bit 2 digital inputs bit 9 bit 13 ilsbi 12 .2. 1 i i dia i converter 19 10 figure 7. unipolar output current 2 i i i dia i converter i.! 10 wil'h input code of 12 offset 1 '000000000 adjust ~ potentiometer for 200" zero volts output 14 output ".iv max rl mds-1240, mdsl-o825, 1035, 1250 figure 8. bipolar output current msb digitial i f t inputs i i i i i bit '2 lsb 29 ground 28 output ovto"vfs 300n mdsl. ,oon mds.,240 ground dia 130 converter 'b ref out 17 10011 } ext to fs "1! adj ref in 31 32 -15v -'5v tho '0011 potentiometer may be omitted if absolute accuracy of full scale is not reouired. in this case pins 17 and '8 should be shortfd and the full scale currenl' will be sima .5%. imds 1240. 'o.2ma '5%1 figure 9. unipolar current output -~ ~~ \ \ \ \ \ \ '\. .......... - page 7 of 8 obsolete
(continued from page 1915) each d i a is housed in industry standard size cases, and each has an internal precision reference. bipolar operation is achieved by external pin interconnection. in normal circumstances, no external components are required for operation into [ow im- pedance loads. designed primarily for pcb mounting, these d/a's may also be plugged into standard dil sockets mounted on 1.8" centers (mds series 2" centers). for ultra-high reliability, this d/a series is optionally avail- able with burn-in extended beyond the analog devices standard of 96 hours at +2soc. notes on fast-settling d/a converters invariably, fast-settling d/a converters use current rather than voltage switching. there are inherent advantages to current-switching converters, since it eliminates an output amplifier. if there is no output amplifier, there is no slew rate limitation which slows settling. the absence of an output amplifier also means there are no overshoot and ringing problems often associated with feed- back amplifiers. the settling time of a current-switching d/a converter, then, is based on: 1. the rc time constant of the converter output. 2. the settling time of the output current change. if the settling time of the d/a converter under consideration is determined by the rc time consta~t, the output capacitance and output impedance become very important. as a typical example in the analog devices' d/a converters, output capacitance is spf, and nominal output impedance is 16sn. for test purposes, the output of these d/a converters are loaded with approximately is0n . (there is no "trick" or "gimmick" in loading the output of the converter; it is done to provide an output voltage of approximately 1.ov to 1.2v.) this loading means rc = 80 x s x 10-12 = dans. since set- tling time is approximately 7 rc, the overall settling time, if determined by the rc time constant, would be 2.8ns. based on this, it becomes obvious the rc time constant of such converters outputs is not the limiting factor in establishing set- tling time. instead, the settling time of the converters is based primarily on the settling time of the overall (outpu t) current change, since the effect of the rc time constant is "swamped." expressed in another way, this means settling time for the mds series converters is relatively independent of load resis- tance, unless substantial load capacitance is present. the set- tling time of the output current, in turn, is based on: 1. the settling time of each switch within the converter. 2. the time skew among the digital inputs which cause the switching action. some manufacturers of fast-settling d/a converters spec set- tling time under the conditions of all digital inputs changing from "0" to "1 h, or vice versa. at first glance, it would appear this is the "worst case" condition for measuring settling time, since maximum current is being switched. unfortunately, this method of specifying neglects an important characteristic of saturated logic. . . the propagation delay for negative-going inputs is different from the delay for positive- -~~--- - - -~- going inputs on all forms of saturated logic. the ttl or dtl driving logic, and the d/a input circuits for current-switching d/a's are subject to this same characteristic. thus, the time skew of the individual current switches within the converter is worse when one or more input bits are out of phase with the others. this is true even for ideal inputs in which the digital inputs arrive simultaneously; if there is time skew among the bit inputs, of course, the problem becomes more pronounced. note, settling times even better than those specified for the mds series become possible if digital input bit arrivals are deskewed. these differences among the switches cause a discontinuity or "glitch" in the output. the true "worst case" glitch always occurs at the switching point of the most significant bit or the center point of the output range, because nearly equal and opposite currents are being switched within the converter. !n addition, all "0" to all "1" switching overlooks the prac- tical aspects involved. there are relatively few times when all of the input bits will be changing from one state to the other on successive input changes; however, the msb will switch out of phase with all other bits each time the analog output of the converter crosses the midpoint. in considering the choice of a "fast-settling" d/a converter, then, the user should look for the following points in the data sheet: 1. if the settling time spec has all bits changing state identi- c~ly, it neglects the phenomenon associated with saturated logic discussed earlier. 2. is the settling time specified with an impractically-iow- impedance load? if the rc time constant of the converter output is the major factor in establishing settling time (because of high output capacitance and lor resistance), a low impedance load helps make settling time look better. a low impedance load means the voltage being dev<:loped at the output is oftentimes too small to be useful. a higher-impedance load which can develop a useable output of 1.ov or more sometimes negates the fast settling time of the spec sheet. a test setup for this worst-case measurement is shown in fig- ure 1. two pulse generators are used to generate the required out-of-phase pulses, and the delays are adjusted for minimum skew. figure 2 is an unretouched photo of the oscilloscope trance of an mds-81s under test. ext. trig mds.o.'s oscilloscope high speeo ttllogicgates or inverters such as '.h04 or 10500 type figure 1. o/a converters 1955 --- ~~ - page 8 of 8 obsolete
|
